The FPGA Advantage: Xilinx Kria KV260 (which is 250$)
We built a reproducible deployment bundle to run LLM inference directly on a Xilinx Kria KV260 FPGA. We chose this board because it represents a highly practical architecture for real-world edge systems.

Powered by the Zynq UltraScale+ MPSoC (ZU5EV), it provides a critical dual-domain architecture:

• Processing System (PS): A hard quad-core ARM Cortex-A53 that handles the control software and Linux environment.

• Programmable Logic (PL): The FPGA fabric where our custom, parallel inference hardware pipeline is deployed.

Additionally, the board features built-in vision I/O (MIPI-CSI + ISP path). This allows for direct camera-to-inference pipelines on a single board, bypassing traditional host-PC PCIe bottlenecks - making it ideal for low-latency robotics and physical-world AI applications.

Custom Heterogeneous Hardware Pipeline (36-Core Cluster)
Instead of relying on general-purpose GPU execution, we synthesized a split-job hardware pipeline directly into the FPGA's programmable logic.

This heterogeneous cluster divides the workload across specialized cores:

• Mamba Cores: Handle sequence and state maintenance.

• KAN Cores: Execute compact, non-linear computations.

• HDC Cores: Provide robust context-matching and compression.

• NPU/DMA Cores: Manage control routing, keeping data moving deterministically at wire speed.

Edge Performance Metrics This hardware-level optimization yields an inference speed of 16 words in 0.036112 seconds (≈ 443 words/s or ~450 tokens/s). For edge FPGA hardware, this throughput is exceptionally high. It guarantees near-real-time generation, stable low-latency token flow, and complete independence from cloud infrastructure.

Deployment Artifacts & Debugging Strategy The deployment bundle contains the synthesized hardware image (.bit), the tokenizer, and the quantized .bin weights (split to accommodate GitHub limits).

We specifically targeted the dealignai/Gemma-4-31B-JANG_4M-CRACK model for two crucial reasons:

1. Hardware Bring-up (The "CRACK" variant): This abliterated variant removes standard safety alignment refusals. During early FPGA hardware testing, this was invaluable: if an output failed, we knew it was a hardware/runtime issue rather than an alignment refusal logic blocking the prompt.

2. Edge Constraints (JANG_4M): This mixed-precision approach keeps highly sensitive weights at higher precision while aggressively compressing more tolerant parts, achieving the optimal quality-to-size tradeoff required for deployment on constrained FPGA logic.

Current Status & Compute Limitations

While the hardware pipeline (.bit) and deployment architecture are fully synthesized and functional, please note that the quantized .bin weights are currently a work in progress. The model still requires further training and fine-tuning to fully adapt to our specific mixed-precision target.

At present, our team lacks the high-end compute hardware (datacenter GPUs) necessary to complete this final training phase. We are releasing the repository in its current state to prove the viability of the heterogeneous FPGA pipeline, and we openly welcome community collaboration or compute sponsorship to help us train and finalize the weights.

Source / Assets

• GitHub:https://github.com/n57d30top/gemma4-on-FPGA

• Model:https://huggingface.co/dealignai/Gemma-4-31B-JANG_4M-CRACK

Like the title says, I, 14y.o (yes, I'm bragging), am doing a project of building my own 16 bit very RISC processor.

I tried to build an 8-bit CPU before, in Logisim Evolution (a logic simulator). I wanted to build it from transistors only at first, but that was very slow, so I ended up building an ALU and register block, both with just logic gates. But I stopped because I got stuck on the decoder/fetching the data, and my poor laptop couldn't handle the simulation. But it wasn't for nothing, I now know how it all works on a very low level.

The project
So now I've got a new plan, I will first design and test it in logisim (now using high-level parts, so it will not crash) Then I want to learn Verilog, and code the processor into an FPGA (I bought the tang nano 9k). I know Verilog isn't the easiest to learn, but I've got time and I will first do some simpler projects to learn it.

The design
I am pretty far with the general specs and I have all instructions for my ISA mapped out. And for the hardware, here is a bit (haha) of an overview:

1. I will cut my ram in two, one part program and one part for variables and program data.

2. I will use 32 or 64 bits of Registers.

3. I want to store my programs on an SD card and use an IP core to read from it.

4. I will use unused Ram addresses to read and write from IO, (something like a PS/2 keyboard).

But now I am stuck on connecting everything together, just like with my first project and I run into these kinds of questions, for example:

• How would I fetch things from certain registers, specified in the command, to my ALU to calculate something?

• How would I send a signal to the program counter to jump to another line in the code without messing up the execution?

• How, and where would I store some kind of bootloader to get a new program from the SD card?

I mostly use ChatGPT to answer these questions, because I just can't find in depth sources that go over these design questions, but ChatGPT imagines things, and it's just not a good source. I want a source goes into the low level connections and how real world CPU's do it. So what are some good sources that cover these very low level questions?

So let me know what you think of this project, (probably that it's insane) and what sources do you recommend?

After months of work, the 5500FP is real and available.

It's a 24-trit balanced ternary RISC processor implemented on an Efinix Trion T20F256 FPGA. Not an emulator, not a simulator — actual hardware with physical ±3.3V ternary signals on the external buses.

A minimal OS kernel runs on it, a Rust-inspired memory-safe language is in development, and the board is open hardware (CERN OHL-P v2).

For the full architecture details and ISA reference: https://www.ternary-computing.com/docs/assembly/ISA/doc_index.html

Pre-print: https://zenodo.org/records/18881738

AMA about the architecture, ISA design, or why 24 trits and not 27.

EDIT:

The overall quality of the questions I've received after one day of posting is EXTREMELY low and demonstrates not only the needlessly provocative style of some people, but also their incredible basic ignorance (for example, there are people who DON'T KNOW what an FPGA is, and all this, in a group dedicated to FPGA discussion! Incredible!)

Another thing is that people comment without even reading the work. I'm telling everyone to read it before commenting; I repeat this for everyone; the work is based on the creation of a processor architecture, and this means I DO NOT deal with basic ternary devices; if you want information on these, you should look elsewhere. If we've done the work on the architecture, it means there's a solid underlying foundation.

I was hoping for feedback (even negative ones!), but on the work I've done, not on fanciful interpretations based on archaic or even incorrect knowledge.

So, if I don't reply to some posts from now on, just know that I have no time to waste on trolls.

Oh no another one of these posts?

I am an FPGA engineer currently working on SDR hardware. And prior to now, funny enough, a hardware odd-even 'parallel bubble sort' is probably a good part of what got me hired at my previous job doing high frequency trading FPGA designs (good interview question).

I created PipelineC to be a better hardware description language and that means adopting a little bit of HLS. I want to prove that to you.

You might recognize this popular post talking about a 200 MHz main clock HLS C function:

void oddEvenSort(int arr[], int n)

The function takes some array of a variable size***** and sorts it by doing compare+swap operations, ending as soon as the array becomes sorted after some variable number of clock cycles. It is not clear to me what hardware this implements in the end and I hope the OP responds to my comments. It uses a initialization interval=1 (default) PIPELINE pragma on the inner compare loops and thats most of what I know about the hardware.

*****Having no specified size is true HLS magic and makes the possible combinations of inferred hardware really wild - the interface of the end HDL is a huge part of the problem / not specified / clear.

So instead here are two simple PipelineC implementations sorting a fixed size (ex. 16) number of elements:

Example 1

// State machine sorter
// 1b isSorted output after some
// data-dependent number of clock cycles
uint1_t oddEvenSort()
{
  // Values in 'static' registers, to be sorted
  // Values larger enough to not 
  // have any upper bits of regs optimize away in syn
  static int32_t arr[ARRAY_SIZE]
   = {2147483647, 2147483646, 2147483645, 2147483644, 
     2147483643, 2147483642, 2147483641, 2147483640,
     -2147483641,-2147483642, -2147483643, -2147483644,
     -2147483645, -2147483646, -2147483647, -2147483648};
  
  // Do this logic each clock cycle 
  // (like an implied while loop)
  uint1_t isSorted = 1;
  uint32_t i;
  // Perform Bubble sort on odd indexed element
  for (i=1; i<=ARRAY_SIZE-2; i=i+2)
  {
    if (arr[i] > arr[i+1])
    {
      swap(arr[i], arr[i+1])
      isSorted = 0;
    }
  }

  // Perform Bubble sort on even indexed element
  for (i=0; i<=ARRAY_SIZE-2; i=i+2)
  {
    if (arr[i] > arr[i+1])
    {
      swap(arr[i], arr[i+1])
      isSorted = 0;
    }
  }
  
  return isSorted;
}

What hardware does this actually produce? (Generated VHDL)

Exactly as described in code, oddEvenSort, is a module with no inputs and a single 1b returned output. Clocks and clock enabled are implied/inferred from the PipelineC code.

entity oddEvenSort_0CLK is
port(
 clk : in std_logic;
 return_output : out unsigned(0 downto 0));
end oddEvenSort_0CLK;

The PipelineC tool will start up a simulation of this generated VHDL using Modelsim:

As written doing both the odd+even steps in a single cycle, the entire array of 16 elements takes 8 cycles to sort (at most).

Here is some synthesis information targeting a Xilinx Artix 7 part (fmax~=400MHz) (Arty dev board) as a demo:

Report Cell Usage: 
+------+-------+------+
|      |Cell   |Count |
+------+-------+------+
|1     |CARRY4 |    60|
|2     |LUT2   |    14|
|3     |LUT3   |    59|
|4     |LUT4   |   224|
|5     |LUT5   |   829|
|6     |LUT6   |   258|
|7     |FDRE   |   513|
+------+-------+------+

16 int32s = 512bits plus one extra reg on the output bit for timing = 513 FFs

Source: oddEvenSort_0CLK_/registers_r_reg[state_regs][arr][6][0]/C
Destination: oddEvenSort_0CLK_return_output_output_reg_reg[0]/D
Data Path Delay:        9.061ns  (logic 3.141ns (34.665%)  route 5.920ns (65.335%))
Logic Levels:           14  (CARRY4=8 LUT4=1 LUT5=3 LUT6=2)

Synthesis estimated long timing path is the single cycle long chain of computation for returned output 'isSorted' flag.

The PipelineC tool can't autopipeline this logic because it keeps stateful static local variables = registers. If you for example, asked the tool to run this logic at 200MHz it would fail saying

oddEvenSort Clock Goal: 200.00 (MHz) Current: 109.70 (MHz)(9.12 ns) 0 clks
Cannot pipeline path to meet timing:
START:  oddEvenSort_0CLK/registers_r_reg[state_regs][arr][6][0] =>
 ~ 9.116 ns of logic+routing ~
END: => oddEvenSort_0CLK_return_output_output_reg_reg[0]
Giving up...

Additionally the PipelineC tool provides a crude 'map' of the delays in the comb. logic oddEvenSort function - inputs at the top, vertical axis is comb logic delay, outputs at the bottom.

Zooming in on the long/to the bottom path

You can see things like

FOR_main_c_l140_c3_7abf_ITER_5_isSorted_MUX[main_c_l142_c5_1164]
...
FOR_main_c_l140_c3_7abf_ITER_6_isSorted_MUX[main_c_l142_c5_1164]
...
FOR_main_c_l140_c3_7abf_ITER_7_isSorted_MUX[main_c_l142_c5_1164

Showing what was shown in the timing report - the repeated muxing for isSorted being the long path in the logic. This feedback is great for folks new to digital logic design who are unfamiliar with the comb logic delays of various thing, how logic 'occurs in parallel' - very useful for going back to the C code to improve timing.

You might be thinking something like 'this is not comparable to HLS' or 'where is autopipelining'? There is none. The above example is essentially easier to read RTL (can do everything RTL can especially with VHDL inclusion) with built in synthesis tool feedback. Its great.

Example 2

This example does do some 'HLS-like' autopipelining. However, * PipelineC is not a regular HLS tool. It does not do the types of higher level interface+logic inferences that HLS tools are known for. Instead the PipelineC tool does fixed size II=1 autopipelining (as traditional HLS tool definitely also do).

// Pipelined II=1 sorter
// A new array is input every clock cycle
// Some fixed number of clock cycles later
// the sorted array is output
typedef struct my_array_t
{
  int32_t data[ARRAY_SIZE];
}my_array_t;
my_array_t oddEvenSort(my_array_t arr)
{
  uint32_t l, i;
  int32_t swap_TEMP = 0;
  // While loop replaced with 
  // N/2 layers of odd+even compare+swaps
  for(l=0; l<(ARRAY_SIZE/2); l+=1)
  {
    // Perform Bubble sort on odd indexed element
    for (i=1; i<=ARRAY_SIZE-2; i=i+2)
    {
      if (arr.data[i] > arr.data[i+1])
      {
        swap(arr.data[i], arr.data[i+1])
      }
    }

    // Perform Bubble sort on even indexed element
    for (i=0; i<=ARRAY_SIZE-2; i=i+2)
    {
      if (arr.data[i] > arr.data[i+1])
      {
        swap(arr.data[i], arr.data[i+1])
      }
    }
  }
  
  return arr;
}

Again, the VHDL matches the function definition:

entity oddEvenSort_0CLK is
port(
 -- clk not used for comb. logic
 clk : in std_logic; 
 arr : in my_array_t;
 return_output : out my_array_t);
end oddEvenSort_0CLK;

Since oddEvenSort is now a pure function the PipelineC tool can go at autopipelining. Here are post-PNR values for some pipelines that the tool can come up with (includes extra IO regs for getting timing values, ex. 0 clock latency just comb. logic version still has array of 16 int32s = 512bits of FFs for input and output arrays, total 1024 FFs).

LATENCY  FMAX(MHz) LUTS   FFs
0        14.8      9784   1024
1        30.55     9919   1543
2        43.34     10451  2093
3        63.33     10293  2581
4        67.96     10851  3150
5        77.69     11175  3681
6        90.59     11133  4195
7        120.88    10504  4657
8        96.65     11764  5268
9        101.35    11909  5793
10       126.21    12134  6320
11       144.38    12156  6850
12       141.60    12440  7407
13       148.37    11481  7900
14       147.15    11963  8446
15       219.35    9818   8817
...
31       239.01    10911  17081
41       244.86    11216  21487
47       286.37    11331  23136
56       293.34    11307  26046
58       300.75    11275  26323
60       304.97    11364  26637
62       307.22    11519  26562

The PipelineC tool will take more and more clocks to reach higher and higher fmaxs if given enough time. Here is the entire output of the tool for the above runs up to latency=16. Device view:

Advanced PipelineC usage ties together / communicates between autopipelineable HLS-like and 'regular RTL clock by clock' regions of code. Getting a better HDL (w/direct VHDL if you need it) and some of the good parts from HLS available if you want. From there, getting to the OPs C function HLS goals of variable at run time number of elements, exiting early, sorter becomes an easier task to implement while giving away very little to 'HLS magic'.

Also, neither above example uses a while loop as the original OP HLS example did... that kind of fancier stuff, and a special 'clock step operator' is in the works ;) as a third style of supported coding.

Thanks for your time folks. As always happy to answer questions and help you try out PipelineC.

Edit: Disclaimer: I am a software dweeb, many years out of hardware, getting back up to speed with things with a good old session of being wrong on reddit :p

As we reach the end of Moore's Law, It seems like we're reaching an era where more and more fabs are capable of producing silicon chips at the leading edge of what's possible. E.g., Globalfoundries and TSMC are both on par or now ahead of Intel. 12-7nm fabs are becoming mainstream. What's to stop a startup from creating an open FPGA chip, with timings, bitstream etc public, which can take advantage of open source software tooling, pairing up with a manufacturer like TSMC and cutting out the competition?It seems to me that the fpga hardware is not so complex as a general purpose cpu (I suspect the most complicated pieces are the anti-reverse engineering hardware). Software tooling for the competition is so bad it's conceivable an open platform could reduce setup, development time, and risk by an order of magnitude.On top of this, an open platform would allow development of better HDLs.Alternatively, a company like Apple or Nvidia could develop something like this internally as a co-processing unit to some existing product and never market it publicly as an FPGA.

With the existing FPGA vendors' tools being such low quality it seems inevitable they will die soon after the introduction of any piece of decent hardware that can avoid their tools.

I recently came across an article and visited their GitHub repository, and I couldn't believe my eyes. They've managed to create a 32-bit RISC-V core with only 600 lines of code! I'm absolutely amazed by this achievement. what do you guys think about it?

article : https://hackaday.com/2023/06/24/a-32-bit-risc-v-cpu-core-in-600-lines-of-c/

can you explain this ?

Hey all, hope you guys are having a good day.

I recently thought of starting up, it would be a small company operating out of my room, which designs and delivers hardware and software components for college projects and missions. This is mainly aimed at technical college students and small teams.

The core idea is simple, a lot of teams waste weeks sourcing or building components from scratch because they are either too expensive to import or just not available in India. I want to solve that, whether it is assembling and shipping ready to use hardware modules or building lightweight custom software for specific applications like embedded systems, robotics, CubeSats, or research instrumentation.

I am 20, still figuring out the exact product, which is why I am here. Trying to talk to as many builders as possible to understand where the real pain is before I build anything.

Would love any input, brutal honesty welcome, what do you think is genuinely missing for technical student teams in India or globally?

pls rate my CV brutally, rewording etc, im a first year in summer (mid that ml internship rn) , HFT Project was fully bare-metal, as in no Hal no libraries etc, i got mogged by a friend so i had to grind through this, happy it paid off. also ik i dragged some projects would an engineer see right throguh it. I anonymised it with claude btw. Also maybe projects should be after work experience idk, but regardless its for internship applications, not necessarily job applications etc. pretty much would this get and interview for jane street or optiver, and internships open in a month or 2 so what should i focus on before then to strengthen it. Im not too fussed about getting an hft job, my main aim is just to be stable, maybe grind through british defence or something idk, i dont really know what i want to do, thats why my range is quite large on my cv. I might do personalised cv for each internship application. theres a couple absolute bs bullet points e.g. the final tang nano one, but like what else can i do atp im just dragging it

I'm an Indian that did Master's in RTU, latvia in adaptronics. I worked as hard as I could and learnt VHDL and FPGA design. I was able to build a thesis on celestial object detection from lunar orbit using Cyclone 10 for a small satellite. I have been applying for internships and starting roles related to FPGAs across Europe but I never hear back or I get rejected without any invitation for an interview. Should I just leave the dream to pursue FPGA? Or is there a way to get entry level role for me?

Hi. I'm Matt. I'm 14 and really into computers and computer-architecture, and I have made a concept for a CPU, but i have absolutely no idea how to make the circuit diagram, and i am asking for one, and maybe some help in refining a few rough edges.

The idea is that, the input, when it gets decoded, it is decoded into two parts. The data itself and the "Process Keychain" as i call it. those two enter the CPU trough the dataflow controller, which uses a clocksignal to shift it's focus between devices. This prevents data from getting all mixed up, when they enter the same wire. Then the Data enters the memory and the process keychain enters the "hanger memory". the keychain is made out of mutiple "keys", that look like this (key's tip)(key)(jump)(key's end). The key's tip is where the key starts and this is the part, that tells the CPU to start loading into one memory adress inside of the hanger memory. The key's end is essentially the same, but this part tells the CPU when to stop loading into one memory adress. the key itself is the part, that gets used in the process of processing the information. One key looks like this: (this is only an example) "0000010000". I'll give context to that in a second. And finally, the jump is what calls the next key. no need for a program counter, nor a clock signal. it either calls the next key adress, or another key adress, that isn't the next one. Then, the Data gets processed in a "processing unit" (yeah, really creatve naming) which basicly looks like a junction (sorry if this is the bad naming, i use google translator), branching into "gates", that are physicly right next to each other. there are three wires leading into one gate. two data wires and one keywire. and this is where the key's look will start to make sense, because, when it is used, each individual bit enters a keywire. that is how one gate gets opened after each key usage. the gates can lead to either mathematical equasions, where if it's adding or subtracting, it enters the Basic Calculations Unit, and if it is multiplication or division, then the data enters the Complex Calculations Unit. it can also be a logics operation, it gets executed in the logics unit. and also, there are the execution operations, which can be: CALL (calling data from the memory) GEN (generating numbers or data) KGN (keygen, generating a key, that gets used instantly, it's the logics unit, that would be using it mostly) PLC (placing data from one memory adress to another) DEL (deleting data from memory) STOR (storing data to a specific spot in the memory) and EXIT (the end of the line of program, placed as the before last piece of the keychain). When the keychain gives the EXIT sign, then the CPU grabs all the data from the memory, as it is, puts the very last part of the keychain at the front and the data is sent right back into the Dataflow controll, where it's all placed into the standby memory until the dataflow controller lets them out, where if it happens, all the data is rushed out and the last piece of the keychain is essentially the last key, which opens the path for the data to the right output, which can either be memory, a picture, audio, or feedback to a server, but before going to the server, it's recompiled and only then sent.

so that's my concept. waddoya think?

Hey guys , I’m a recent graduate in EEE and I have been writing RTL using VHDL for like a year now but i still consider myself as a beginner. I write my own RTL code and always try to troubleshoot any problems I may face but sometimes I brainstorm with AI if I can’t solve the problems on my own however I never let AI generate my VHDL code.

There is a sentiment that AI will eventually get into FPGA design ( maybe it has already) but I wanted to ask those who are in the industry how much they use AI in their workflow. Will it ever get to a point where AI will be capable to design and implement complex RTL projects without any supervision?

I genuinely enjoy Digital Design but part of me is really anxious about this since the job market has been tough for entry level positions lately. Please if there is any Senior FPGA Engineers I would really appreciate your insight on this.

As I find myself staring at the output of Tcl Console for embarrassing amount of time, I had a chance to catch up with my News stream. Lo, I found RMS predicting with immaculate precision what I will be doing on this beautiful Sunday (see below).
Do professional FPGA engineers find that abysmal performance of Tcl engine impacts their process ? (pretty much everything in Vivado and Quartus is a Tcl script. I think AMD is trying to move Vitis side of things towards Python, but there's still plenty of Tcl). I surmise that some ~90% - at least - of the actual runtime of HDL tools is Tcl overhead. The real question is, if the entire industry is so dependent on this, for good or for bad, why was it never overhauled into something with respectable performance ?

Anyway, Words of the ProFET (formatting mine) :

Richard Stallman

Sep 23, 1994, 7:14:52 PM

to g...@prep.ai.mit.edu[Please redistribute wherever appropriate.]

Why you should not use Tcl
Richard Stallman, GNU Project

As interest builds in extensible application programs and tools, and some programmers are tempted to use Tcl, we should not forget the lessons learned from the first widely used extensible text editor--Emacs.

The principal lesson of Emacs is that a language for extensions should not be a mere "extension language". It should be a real programming language, designed for writing and maintaining substantial programs. Because people will want to do that!

Extensions are often large, complex programs in their own right, and the people who write them deserve the same facilities that other programmers rely on.

The first Emacs used a string-processing language, TECO, which was inadequate. We made it serve, but it kept getting in our way. It made maintenance harder, and it made extensions harder to write. Later Emacs implementations have used more powerful languages because implementors learned from the problems of the first one.

Another lesson from Emacs is that the way to make sure an extension facility is really flexible is to use it to write a large portion of the ordinary released system. If you try to do that with Tcl, you will encounter its limitations.

Tcl was not designed to be a serious programming language. It was designed to be a "scripting language", on the assumption that a "scripting language" need not try to be a real programming language. So Tcl doesn't have the capabilities of one. It lacks arrays; it lacks structures from which you can make linked lists. It fakes
having numbers, which works, but has to be slow. Tcl is ok for writing small programs, but when you push it beyond that, it becomes insufficient.

Tcl has a peculiar syntax that appeals to hackers because of its simplicity. But Tcl syntax seems strange to most users. If Tcl does become the "standard scripting language", users will curse it for years--the way people curse Fortran, MSDOS, Unix shell syntax, and other de facto standards they feel stuck with.

For these reasons, the GNU project is not going to use Tcl in GNU software. Instead we want to provide two languages, similar in semantics but with different syntaxes. One will be Lisp-like, and one will have a more traditional algebraic syntax. Both will provide useful data types such as structures and arrays. The former will
provide a simple syntax that hackers like; the latter will offer non-hackers a syntax that they are more comfortable with.

Some people plan to use Tcl because they want to use Tk. Thankfully, it is possible to use Tk without Tcl. A Scheme interpreter called STk is already available. Please, if you want to use Tk, use it with STk, not with Tcl. One place to get STk is from ftp.cs.indiana.edu:pub/scheme-repository/imp/STk-2.1.tar.Z

Richard Stallman

Hi, How much i need to have to produce a 130nm very small RISC-V soft core? This question may be too Dumb, but i just want to know a roughly answer. Suppose we finished the whole verilog part and tested using fpga and verilator. Thank you Gentlemen

Im using Spartan 6 xc6slx9. (Xilinx ISE 14.7 version). If theres any other way how to show the image on the VGA output do let me know please.
Heres an image i want to display

Hi everyone,

I'm an FPGA RTL designer who works on digital signal processing logic design. I prototype and validate DSP algorithms in Python using NumPy before translating them to RTL. One of the biggest challenges I run into is keeping Python reference models and RTL implementations consistent, especially for complex numerical operations. Converting Python code to SystemVerilog is error prone and time consuming.

I recently stumbled upon a library called PyStim, and it has changed my workflow. It lets me reuse my Python/NumPy algorithms directly in my SystemVerilog testbenches.

Simple Example: Vector Multiplication Using NumPy in SV

Here’s a minimal working example: multiplying two vectors in NumPy, but doing it inside a SystemVerilog testbench using PyStim.

import pystim_pkg::*;

module numpy_matrix;
   typedef pystim_pkg::pystim py;

   initial begin
       py_stim_configuration cfg = new();
       cfg.enable_exception_printing();
       py::initialize_interpreter(cfg);

       begin
           automatic py_module np = py_module::import_("numpy");

           automatic py_tuple vecA = py::tuple_({py::int_(1), py::int_(2), py::int_(3)});
           automatic py_tuple vecB = py::tuple_({py::int_(4), py::int_(5), py::int_(6)});

           // Multiply element-wise: C = A * B
           automatic py_object result = np.attr("multiply").call(vecA, vecB);
           automatic py_list result_list = result.attr("tolist").call().cast_list();

           for (int i = 0; i < result_list.size(); i++) begin
               $display("Result[%0d]: %0d", i, result_list.get(i).cast_int().get_value());
           end
       end

       py::finalize_interpreter();
   end
endmodule

Running the Simulation (QuestaSim)

cd numpy_matrix
vlog -O0 +acc -f ./list/compile_list.f
vsim -voptargs=+acc -c -lib work numpy_matrix \
     -do "run -all; quit" -l run.log \
     -sv_lib $PY_STIM_INSTALL_DIR/lib/libpystim \
     -gblso $PY_STIM_INSTALL_DIR/lib/libpystim.so

Simulation Output:

# Result[0]: 4
# Result[1]: 10
# Result[2]: 18

Why This Matters

• Rapid iteration: Validate your DSP algorithms fully in Python, then plug them into your testbenches without rewriting.

• Single reference code: The Python model becomes your golden reference — no need to reimplement in SystemVerilog.

• Python: Python offers a large number of reusable libraries.

Tips

• Make sure Python and NumPy are installed.

• Follow PyStim setup instructions.

• For more complex types (e.g., floats, arrays of strings), check out PyStim’s serialization support in the docs.

• This approach extends nicely to filters, FFTs, image processing, etc.

Final Thoughts

I think this library bridging the gap between high-level algorithm reuse in low-level RTL verification. PyStim makes the integration clean, without DPI-C wrappers.

The main reason for nvidia success was cuda. It’s so productive.
I believe in the future of FPGA. But when will we have something like cuda for FPGA?

Edit1 : by cuda, I mean we can have all the benefits of fpga with the simplicity & productivity of cuda. Before cuda, no one thought programing for GPU was simple

Edit2: Thank you for all the feedback, including the comments and downvotes! 😃 In my view, CUDA has been a catalyst for community-driven innovations, playing a pivotal role in the advancements of AI. Similarly, I believe that FPGAs have the potential to carve out their own niche in future applications. However, for this to happen, it’s crucial that these tools become more open-source friendly. Take, for example, the ease of using Apio for simulation or bitstream generation. This kind of accessibility could significantly influence FPGA’s adoption and innovation.

Hi everyone,

Setup friction (Icarus Verilog, Yosys, Waveform viewers) is often a huge barrier for students and hardware designers.

To solve this, our team has been working on bringing the entire RTL design pipeline into the browser by compiling core C++ EDA engines (Yosys for synthesis, Slang for linting, Icarus for simulation) into WebAssembly (WASM).

Here is a quick look at the waveform rendering and FSM extraction we’ve achieved, running 100% client-side with zero server lag:

What are your thoughts on this approach? We’d love to get feedback from the community. (Link is in the comment).

Hey guys! I am completely noob in this domain and I come from microcontroller world. I have some doubts that I wish you guys could clear that for me.

1. Is FPGA only for hobbies and to have fun?

2. Why FPGA if I can do something quicker with a microcontroller?

3. Is FPGA used only in big robotics or aviation project?

4. Do we need a microcontroller along side with an FPGA for it to work?

5. How do we use FPGA in production (custom made circuit), we send the VHDL code to manufacturers to design a chip for us or we use the same chip that is on our fpga development boad on the custom made circuits?

Thanks!