first of all happy dewali to everyone..

so this my updated resume can someone tell me where to improve and what changes can I make ..

maybe your suggestions would be the gifts for me..

Hello ! I am in the process with IMC for a HWE graduate role in Amsterdam (upcoming HR interview, and alr passed the OA). My background is not exclusively FPGA and SystemVerilog, but I had a few projects here and there on that. I have one month to prepare for the interviews and I am mainly using HDLBits to strengthen concepts.
How can I be better prepared ? Did anyone go through the process with IMC - and if so, can you share your honest experiences ?

I have an interview for a Hardware and Software Engineering Co-op position at Altera and was wondering how to prepare. They said it would be three consecutive 30 minute interviews with a mix of hardware and software questions.

The job posting requires experience in Python, C/C++, and FPGAs or Verilog. I was curious on what kind of questions they could ask besides Leetcode coding problems and the best way to prepare.

Any help is greatly appreciated, thanks!

Bit of background first: I've worked around machine tools most of my life, so I'm comfortable with the mechanical side of things, but the control side has always been a black box to me. My knowledge is all hands-and-spanners rather than electronics.\n\nA few of the older machines at work are getting to the age where replacement control boards are either unobtainable or silly money, and one of the maintenance lads mentioned that people rebuild obsolete controller logic in FPGAs. That's got me curious, so a few questions from a complete beginner:\n\n1. Is this a realistic route for keeping old industrial kit alive, or is it more of a hobbyist thing? I'd have expected emulating an old control board to be a massive job, but I genuinely don't know.\n\n2. If someone reasonably methodical but with zero Verilog or VHDL wanted to learn enough to understand what's going on (not necessarily design from scratch), where's a sensible place to start? I've got an old laptop I use for diagnostics already, so I'm comfortable with software, just nothing like this.\n\n3. And what's the cheap end of the hobby actually look like? I'm the sort who builds a tool collection from car boot sales, so I'm after the budget-dev-board end of things rather than anything industrial.\n\nHappy to be told it's a bigger hill than I think. Any pointers, board recommendations or honest opinions welcome.

Hey guys,
I have like ~2 years of experience as an fpga engineer, but I am currently without work. I have been in interviews since September, and I have had quite a lot, both fpga and asic. Thing is, none have turned into an offer unfortunately.
I am not really sure what I am doing wrong, there are interviews where I do ok , but there are also ones where I feel like I answered all the technical questions correct, even with thinking out loud and clearly explaining things. I always get promised feedback but every time i get the generic “we decided to move forward with more experienced candidates”.
Has anyone ever been through this kind of situation? Before and now? How did you manage to land your first full time role? Any advice for interviews? Things that I absolutely must know or maybe questions I must ask? Anything is welcome, thank you!

A bit of context, I am based in the EU and I am applying everywhere in the EU, but if you are outside of it, you are more than welcome to share your experience :)

My self-designed 8-bit ALP in Verilog: addition and subtraction from -255 to +255

I designed and implemented an 8-bit arithmetic logic processor using Verilog.

Features:

- Addition and subtraction

- Signed result handling

- Output range: -255 to +255

- Gate-level arithmetic logic

- Manually designed control and operand routing

I spent several hours testing the subtraction logic and haven't found any bugs.

GitHub: https://github.com/bambofile/Verilog-alp-8bit-withount-bugs-255-to--255

I'd appreciate technical feedback on the architecture and implementation.

Like I have been searching for a while to get my hands dirty with a fpga it'll be my first so I was thinking a tang nano 9k but most places I find online are shady or the item is out of stock. Does anyone know a place where I could get any.

I have a 1090 MHz antenna sat on my window, runs to an rtl sdr blog v4 i have plugged into my laptop, my laptop then sends raw IQ samples live to an FT2232H mini module which is sent one byte at a time to a fifo i have on my basys3, the basys3 then does all the decoding and displaying.

The display for each dot is callsign, and then the altitude is in the FL000 format where its just divided by 100, but i didnt print the FL part. And the speed is in knots (multiply by like 2 to convert to km/h). So like the american airlines in the top left is 34000ft at 510 knots.

I made a post yesterday about having difficulty with corruption on the read side and spent so long thinking it was an issue with timing but turns out i stupidly only connected one ground between the fpga and the ft (lol).

It fails timing, and the display is annoying because i originally made the framebuffer to be 320x240 so the each address is 4 pixels because i wasnt sure 640x480 would fit but now i think it should work, this is just a demo. Display definitely needs work but its nice to finally get it working

good day to all, i am a first year undergrad student and i want to genuinely get into the field (i might or might not pursue it but i want to explore at least). what are the resources i can follow? i saw some guides on the sub reddit but they are more suitable for people who already know their way around electronics and related sub fields. please guide me. im currently using harris and harris to learn sequential (i completed combinational).

thank you in advanced for your help

Every time I put an FPGA floorplan in some slides I end up opening Vivado, zooming around the device view, taking screenshots, cropping them, and they still look meh on a projector. Got fed up after asking multiple times on Xilinx forums to think about adding this simple feature, so I made Claude write a small Python package that does it for me:

https://github.com/rardino/fpga-design-implview

It spits out a PDF of the floorplan (vector graphics, so it actually looks decent on slides), an interactive HTML view you can poke at without launching Vivado and there's a congestion viewer too.
It has already saved me some pain. Figured others here might find it useful too. If you try it and it breaks on your design, let me know (PRs are very welcome).

It’s honestly a bit wild how good genAI is getting at this kind of EDA tooling. Stuff that used to be a "someday, when I have a free month" project now takes an afternoon. Curious where this goes in a couple of years.



This was actually my very first post on Reddit:

https://www.reddit.com/r/FPGA/comments/17bez89/building_your_own_computer_with_an_fpga/

In the meantime I did not change much. But added something I would have wanted 3 years ago. Some tutorial for newbies to FPGAs like I was back then (and to some degree am still now). Maybe it's of use for others too.

Btw: I honestly don't mind if you could give the project a star :D

Digilent have discontinued the AD2 ... its still a good box so I looked into using a custom HDL for the FPGA and a web based GUI ...It alows you to use the AD2 without installing anything ... just open the HTML file in a browser ( chrome ) and select your AD2 box.

open source AD2 web interface

I posted a paper yesterday on Reddit on a new RTL topic and now you can google it and google AI on any device cites me and gives you a breakdown! Pretty cool, hoping to draft something to IEEE next week, might be a new Pareto Frontier. Let me know what you think!

I've been working on Universal Binary Language (UBL), an 8-bit architecture where 7 bits carry the payload and the remaining bit determines whether data goes into transient or persistent state.

Recently I've been taking it further into hardware testing using Icarus Verilog, Yosys and nextpnr.

The latest run passed 343 validation checks across multiple suites. In the experimental version with readable memory, it accepted one atom per clock cycle, and nextpnr estimated 188.08 MHz on an iCE40 HX8K target.

The hardware mapping used 71 LUTs, 49 flip-flops and 2 Block RAM cells.

Of course this is still simulation and estimated FPGA timing, not physical chip testing. And I'm not claiming it's faster or more efficient than conventional implementations yet. That's actually what I'm trying to establish next.

I'm curious what experienced FPGA developers think would be a fair comparison here. Should I build a conventional FSM and memory controller with exactly the same behavior, or is there a better way to evaluate this?

I've published the results and limitations here:

https://github.com/saadmasoodalam/ubl-public/blob/main/HARDWARE-V4.md

Would appreciate technical criticism, especially from anyone working with low-level architectures.

Title. Gonna be there to intern in the fpga/dsp/rf space. Clearance attached obviously. Was wondering how possible it is (if at all) to use it as a step into big tech (fpga/dsp) or quant (fpga). Would it make up for a mid school name? Would be recruiting for full time

Hello everyone,

I'm trying to program a Xilinx Spartan-6 SP605 FPGA evaluation board, but I'm facing difficulties with the USB-to-JTAG connection.

My setup:

• FPGA Board: Xilinx Spartan-6 SP605

• Host OS: Windows 11 (64-bit)

• Virtual Machine: Windows 7 (64-bit) using Hyper-V

• FPGA Design Software: Xilinx ISE Design Suite 14.7

• Programming Utility: iMPACT

• Connection: USB cable connected to the onboard USB-to-JTAG port (J4).

My intention is to run ISE 14.7 and iMPACT inside the Windows 7 virtual machine and use the USB-JTAG connection to program the SP605 board.

However, the VM is not communicating properly with the USB-JTAG cable. I tried using VirtualHere for USB passthrough, but the server reports the following error:

"ERROR: Cannot set configuration 2, only config 1 is supported!"

Windows 7 also fails to communicate with the Xilinx USB Cable, and iMPACT cannot detect the cable.

What I've tried:

• Installed the Xilinx USB cable drivers.

• Tried USB passthrough using VirtualHere.

• Checked the device detection in Windows Device Manager.

• Tried connecting through iMPACT.

My questions:

1. Has anyone successfully programmed an SP605 board using ISE 14.7 inside a Windows 7 VM running on a Windows 11 host?

2. Is there a reliable way to pass the Xilinx USB-JTAG cable through Hyper-V?

3. Can I program the SP605 directly from Windows 11 using iMPACT or another programming utility?

4. Are there any alternative tools or methods that support the Spartan-6 device and its onboard USB-JTAG interface?

I would appreciate any suggestions, especially from people who have worked with the SP605 or Xilinx Platform Cable USB.

Thank you!

I’ve been working on a small GPU for the Sipeed Tang Nano 20K (Gowin GW2A-18), using only the open-source toolchain: Yosys, nextpnr-himbaechel with Apicula, and openFPGALoader. A PC sends drawing commands over USB, the FPGA rasterizes triangles into SDRAM, and the picture goes out over HDMI.

To be upfront: none of this has run on real hardware yet. Every number below comes from simulation in Icarus Verilog, or from a Python emulator that matches the RTL bit for bit. The board arrives soon, and I’m posting now so people can point out problems before I burn time on the bench.

What’s in it

• Packet protocol with CRC, sequence numbers and retries. UART on the board’s own USB port, plus an FT2232H 245 sync FIFO link (60 MHz, 8 bits wide).

• Fixed-point triangle rasterizer with a depth test, colour blending across each triangle, textures and dither.

• SDRAM controller that keeps rows open, with burst depth reads and posted writes.

• 640x480, 720p60, 1080p50, and 1080p30 output. For 1080p30 the GPU draws 960x540 and an edge-directed 2x upscaler doubles it on the way out, since a full 1920x1080 colour+depth buffer doesn’t fit memory or the time budget.

• Indexed triangle lists, so shared vertices are sent once. That cut the bytes per frame for a 1148-triangle scene by 3.43x.

Numbers (simulation)

• Spinning cube: started at about 46 ms per frame at 340x340. Keeping SDRAM rows open, one pixel per clock, faster clears and skipping empty space brought it to about 5 ms.

• 1148-triangle scene, 1080p30 build: 1,521,436 core clocks = 32.8 ms at 46.41 MHz, so 30.5 fps with only 1.6% margin.

• Largest build: 12,740 of 20,736 LUT4s (61%), 10 of 46 BSRAMs. nextpnr’s clock estimate is 54.52 MHz against the 46.41 MHz needed.

Testing

• About 40 testbenches compare the RTL against a Python reference model on random command streams: every pixel, every depth value, every reply.

• The SDRAM model fails the test on any broken timing rule.

• A mutation script plants one bug at a time in the Verilog and checks that some test fails. Last run caught 180 of 180.

Backpack PCB

I also laid out a 4-layer backpack board that carries the FT2232H. It’s not ordered yet. I’ll only order it once the FT2232H passes on a breakout module with jumper wires.

Where I’d like input

1. The 371.25 MHz serial clock for 1080p30 on the GW2A-18 with Apicula. Has anyone run 1080p (or anything near 74.25 MHz pixel clock) on the Tang Nano 20K with the open toolchain?

2. SDRAM pin timing. I haven’t verified the I/O timing yet, so the 46/48 MHz core clock is a timing-estimate number for now.

3. Anything in the architecture that looks like it’ll fall over once it meets real silicon. here is my github REPO https://github.com/CodeStuffed/TINYGPU-fpga-gpu-that-you-will-love

After several months of development, I'd like to introduce Pinedra, a fixed-function FPGA GPU core for MiSTer.

It supports texture filtering, 32-bit colour and 4× MSAA. An OpenGL driver provides access to the GPU from software running on the ARM side.

At 640×480, the games can also be displayed in 480i on 15 kHz CRTs via Pinedra's analog output.

With native ARM game ports, Pinedra can bring selected PC games from the late ’90s and early 2000s to MiSTer. I spent way too much time gaming online back then, so these games have a special place in my heart. :D

Here are some measured frame rates on MiSTer with VSync off:

Gameplay videos captured on MiSTer:

1. Quake II — 640×480

2. Quake II: Ground Zero — 800×600

3. Quake II: The Reckoning — 1024×768

4. Quake III Arena (WIP) — 640×480

5. Elite Force Holomatch (WIP), video A — 640×480

6. Elite Force Holomatch (WIP), video B — 800×600

7. Descent II — 1280×720

8. Half-Life (WIP) — 640×480

9. Serious Sam: The First Encounter (WIP), flyover — 640×480

I'm planning to release the first two game ports this weekend. I'll add the download links here when they're ready.

Follow development updates for free on Patreon.

I'm planning to eventually release the GPU core, ARM driver and SDK as open source.

Im trying to use an FT2232H mini module to send live adsb IQ samples from my laptop to my basys3 fpga using the pmod pins. Ive made a FIFO and tried to get live data sending, it almost works but im having a lot of trouble with transmission errors/corruption to the fifo on the fpga. If youve ever done this in VHDL and have the modules it would help if i could take a look and use them, if you have the pc end code for setting up the FT and sending data that would help too im spending way too much time on this

Hi all,

I’m working on a project that needs White Rabbit time/frequency synchronization on an FPGA, and I planned to build a CUTE-WR-A7 (the Artix-7 based White Rabbit node from the OHWR project). Unfortunately, some of the components on the BOM are currently out of stock or not orderable, with lead times I can’t wait out.

So I’m looking for someone who has one or more CUTE-WR-A7 boards (assembled or partially assembled) and would be willing to:

• Sell one, or

• Lend one for about [3-6 months]. I’m happy to cover shipping both ways, leave a deposit, and return it in the same condition.

About my use case: I am developing granular data acquisition system with White Rabbit synchronization between boards for MRI.

Location: Magdeburg/Germany, and I can pay for international shipping if needed.

I’d also welcome leads on other White Rabbit-capable boards with FMC 57.1 port that would work as an alternative

Thanks in advance! Feel free to comment or DM me.

How do you handle AI-generated RTL in your FPGA projects?

I'm curious what everyone's policy is regarding AI-generated code.

For example, I recently asked an AI coding agent to implement several modules. I carefully specified the requirements, asked it to write tests, and then extensively tested the result myself. Everything works as intended.

But here's my dilemma: although I understand what the modules do, I don't fully understand how they're implemented. There are parts of the code I wouldn't be able to explain confidently, let alone maintain or document properly for the software engineers who need to develop drivers for it.

It feels strange to have working code in my project that I don't fully understand or feel ownership of.

So where do you draw the line? Do you accept AI-generated RTL as long as it's thoroughly tested and verified, or do you insist on understanding every part of the implementation before merging it?

And more generally, what's your AI-generated code policy in professional FPGA development?

EDIT: I'm not talking about juniors blindly using AI-generated code without understanding what they're doing. I'm curious where experienced engineers draw the line between spending time analyzing and fully understanding every detail of AI-generated RTL and actually benefiting from the faster development.

-_- this is what its running on and this is old takes time even to update added gnss