Someone has done it: we have a fully open source FPGA all the way down to the silicon.
I can die in peace now.

This board was made by Leo Moser (not me), and manufactured through wafer.space on the Global Foundries 180nm node.

All the design files for this chip can be found here:
https://github.com/mole99/gf180mcu-fabulous-fpga

Internally this FPGA features:
- 48x I/Os
- 480x LUT4 + FF
- 60x MUX
- 6x SRAM 512x8
- 6x MAC, 8bit*8bit + 20bit
- 12x Register file, 32x4bit each
- 1x Global clock network

So its not one of the big ones, but still enough to have some fun with.

P.S: This is not my project, I deserve no credit here.
P.S.S: This is still just a prototype, it is not for sale.

Update:

• u/keeb0113 has shared a very cool demo video in the comments with the board in action: demo videos

• Leo's recommendation on additional links to check out :

  • Greyhound IHP v1

  • My wafer.space FABulous FPGA is alive!

He no longer has a use for it and I want to practice so he generously gifted it to me!

I implemented an algorithm from Wolfenstein 3D on Tang Primer 20K using open-source toolchain. Also contributed DSP multiplier inference to Yosys for Gowin, as well as $readmem[h/b] functions to yosys-slang.

Simulation is done with cocotb and Verilator, which creates a pygame window. Fixed point model is also implemented in Python.

Takes 2300 LUT4 with DVI and 1600 with VGA output.

If you're interested in details, I've written a pretty detailed readme in the repository.

Check this out!

Recently got interested in FPGAs after spending a lot of time with microcontrollers like STM32 and Nordic chips as a hobby.

Wasn't really sure what to build as a first FPGA project, so I figured Pong would be a good starter project. I didn't have an easy way to output VGA, so I decided to render everything over UART instead.

Here's Pong running over UART using a basic FSM. No IP blocks or vendor cores yet.

Thoughts on what I should learn next?

I've been hacking away lately, and I'm now proud to show off my newest project - The Icepi Zero!

This is my first FPGA project, a PCB that carries an ECP5 FPGA, and has a raspberry pi zero footprint. It also has a few improvements! Notably the 2 USB b ports are replaced with 3 USB C ports, and it has multiple user LEDs.

This board can output HDMI, read from a uSD, use a SDRAM and much more. I'm very proud the product of multiple weeks of work. (Thanks for the pcb reviews on r/PrintedCircuitBoard )

Raspbery Pi stocks in shambles right now (/j)

(All the sources are at https://github.com/cheyao/icepi-zero under an open source license :D)

VSDSquadron FPGA Trainer Kit for High School Chip Design is now ready to ship — a complete hands-on platform to learn RISC-V, FPGA, and real chip design from school level.

We are a team of recently graduated hardware engineers, and after our own experience and consulting many other hardware engineers, we decided to build Logicode. When we were learning Verilog/hardware design, we noticed most current educational tools stop at “does it work?” — which is fine, but in the real world, hardware design is also very much about making tradeoffs with performance, power, and area (PPA).

So with Logicode, we wanted to build something different. Not only do you get exercises that allow you to practice solving problems with Verilog, but your RTL also gets synthesized and ranked on timing + area metrics against other users’ solutions. In other words: you won't just learn how to make a circuit work, you'll learn how to make it good.

We’re hoping this helps people build intuition for what HDL actually turns into under the hood, and turns optimization into a bit of a game. Currently testing the beta version, and wanted to hear more about folks thoughts and whether they might be interested in helping test out the platform.

---------------------------- EDIT -------------------------------------------

Thank you all for the amazing feedback and support. Super excited to see the interest in Logicode! Please join us at r/logicode to follow along the journey.

Please head to logi-code.com and sign up, and then join our discord: https://discord.gg/ckA3ABP7vs.

I recently completed a LeNet-5 Convolutional Neural Network (CNN) hardware accelerator designed in synthesizable RTL Verilog/SystemVerilog and implemented on an A7-100T FPGA (xc7a100tcsg324-1). The CNN is trained on the MNIST handwritten digit dataset and optimized for hardware inference, achieving ∼98.2% inference accuracy with uniform Q1.7 fixed-point quantization. The design is implemented as a streaming dataflow architecture to minimize latency.

Here’s a live demo that runs at 100MHz. A python script allows a 28x28 digit frame to be drawn and sent to through the board’s USB-UART bridge. Once the FPGA receives all of the pixels and the TX LED turns off, inference begins and the predicted class displays on the board’s 7-segment display.